1. Field of the Invention
The present invention relates to a semiconductor integrated circuit in which memory cells including transistors and capacitors (capacity elements) are formed on the major surface of a semiconductor substrate, also relates to a method of manufacturing the same.
2. Description of the Related Art
Technologies of integrating memory cells having MOS transistors and capacitors on the major surface of a semiconductor substrate are conventionally known. In this conventional semiconductor integrated circuit, to dielectrically isolate the memory cells, a LOCOS (Local Oxidation of Silicon) structure, a field-shield structure, and a trench structure are used. The LOCOS structure dielectrically isolate the memory cells by using a thick field oxide film, as disclosed in Japanese Patent Publication No. 50-1379 (Application No. 43-44309, Patent No. 789648). The field-shield structure dielectrically isolate the memory cells by fixing an electrode of a MOS structure at a reference potential and cutting off a parasitic MOS transistor, as introduced in "Nikkei Microdevices", June, 1992, pp. 84-88. The trench structure dielectrically isolate the memory cells by forming a trench in the major surface of a semiconductor substrate between element active regions in which memory cells are to be formed and filling the trench with an insulator.
These dielectric isolation technologies pose the following problems when realizing a high-density, large-scale semiconductor integrated circuit. In the LOCOS structure, if a thick field oxide film is formed to ensure sufficient dielectric isolation, an extension at the end portion of the field oxide film, what is called a "bird's beak", is formed. Additionally, since a high-concentration impurity diffuses from the lower surface of the field oxide film to the element active region, the circuit element function in the element active region is decreased by a narrow-channel effect on the influence of the diffusion. These make a high density difficult to obtain. In the field-shield structure, since the field-shield structure itself is a MOS transistor structure, down-scaling and miniaturization are limited by a short-channel effect. Especially, in a DRAM, since it is necessary to dielectrically isolate a large number of capacitors, while avoiding the formation of very small leakage current paths between them, it is difficult to decrease the dielectric isolation width. In the trench structure, since a leakage path is formed by mechanical strain near the bottom surface of the trench, the electrical characteristics of a semiconductor integrated circuit having memory cells of a DRAM on a large scale are degraded.
These conventional dielectric isolation technologies are unsatisfactory to realize a future high-density, large-scale DRAM in which memory cells having MOS transistors and capacitors are arranged in a matrix manner on one major surface of a semiconductor substrate and dielectrically isolated from each other.